Researchers at MIT have developed a 36-core processor

We are more or less familiar with the presence of mobile devices these days that sport dual-core and quad-core, and in some cases, octa-core chipsets, but what about this new prototype from the brains over at MIT? They have apparently come up with a 36-core computing chip that will make use of a system known as ‘network-on-a-chip’, allowing data to pass between cores in a far faster and more efficient manner compared the the traditional bus layouts that are in use at the moment. While a standard multi-core processor will send all of its data through a single wire, allowing only a solitary core to communicate at a time, which means a growth in the number of cores would see these cores meeting a bottleneck as they wait for their turn to access to the bus to transfer data.

Researchers at the Massachusetts Institute of Technology have developed a 36-core processor in an effort to find new ways to eke more performance out of chips. The chip is designed to reduce the number of cycles required to execute tasks by enabling data transfers between cores and cache in a more coherent manner, said Bhavya Daya, a Ph.D. candidate in MIT’s Department of Electrical Engineering and Computer Science. With the help of mini-routers, MIT researchers have devised a novel way to reroute data packets to free up bandwidth within multicore chips, Daya said. The research could benefit highly parallel applications such as financial analytics and particle simulation studies. The chip research revolves around implementing a “shadow network” so cache in specific cores can anticipate data packets. Large data sets received by chips are typically broken down and migrated across multiple cores, which have their own cache to temporarily store data. If a core needs specific data, then requests are broadcast across cores in a chip. But the broadcasts take up unnecessary bandwidth and through the research, the MIT researchers are enabling more direct communication between cores and cache. The goal is to “force” ordering within a multicore chip so the cache can anticipate and prioritize data packets, Daya said.